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Silicon Image's camerIC™ family of camera processor IP cores deliver low-power, high-resolution video and still image capture for digital cameras, smartphones, netbooks, and other mobile devices. The camerIC high-performance camera pipeline includes image processing, scaling, and compression functions, and is also capable of integrating many additional features. Its image signal processor (ISP) supports both simple CMOS sensors with no image pre-processing and those with integrated YCbCr processing. Available for 2D and 3D applications, Silicon Image's camerIC family of IP cores is now in its fifth generation. Since 2002, over twenty camerIC-based camera designs have been delivered for use in system-on-a-chip (SoC) application processors
Low-Power Camera Processor for Mobile 3D and High Resolution Still Picture and Video Applications
The camerIC-3D/64MP IP core supports 3D and high-resolution still picture and video applications. It leverages production-proven technology to offer a cost-effective, low-power camera processor IP design that is compatible with most CMOS sensors to ensure ease of integration. The camerIC-3D/64MP IP core supports resolutions ranging from 3MP up to 64MP (8Kx8K) in a single low-cost/low-power design. It also supports pixel rates up to 2x 300 megapixel/sec, enabling high frame rates for superior image resolutions.
To effectively deliver resolutions above 12MP, the camera processor features sophisticated bad pixel detection/correction and noise reduction techniques to ensure image quality even when paired with the low cost, high-resolution CMOS sensors commonly found in mobile devices. The camerIC-3D/64MP IP core also supports wide dynamic range processing and digital image stabilization, along with an extensive set of standard features. In addition to its DSC capabilities supporting up to 64MP resolution, the camera pipeline has the imaging bandwidth to support 3D 1080p resolution at up to 120 frames per second and beyond. 4Kx2K (8MP) resolution at 30 frames per second will require as few as 660k gates to implement in hardware while consuming as little as 125mW of power (40/45nm process). The camerIC hardware design is optimized to consume as little as 1 MIPS per frame of CPU bandwidth-making the camerIC-3D/64MP one of the industry's highest performing camera processors. The camerIC-3D/64MP IP core supports both parallel and serial input interfaces compatible with most CMOS sensors and several CPU and memory system interfaces. The CMOS sensor sends data to the ISP via parallel interfaces supporting ITU-R BT 601 and 656 compliant video data. In addition, several serial interfaces are supported including baseline compliant CCP-2 mobile imaging architecture (SMIA) and camera serial interface (CSI-2) MIPI. When communicating with a CPU or memory, 64bit AXI, 32bit AHB and BVCI/PVCI are supported.