• Video Decoder IP Cores

  • videodecoder_solutionsSilicon Image Video Decoder IP Cores are designed as system-on-a-chip (SoC) solutions for TV and home theater markets at the lowest possible silicon costs. Its interfaces are optimized for easy integration using the standard on-chip bus approach. This dramatically reduces the integration effort and enables fast time-to-market developments.

  • cineramIC 4K-3D & Multi-Channel HD Video Decoder IP Core 

    Scalable Multi-Standard and Multi-Stream Video Decoder (H.264, MPEG-1/2, VC-1, JPEG) with MVC Support for 3D Video Applications



    The cineramIC 4K-3D Video Decoder is capable of decoding video streams up to 4K-3D and 16 HD streams. It is one of the highest performing synthesizable cores on the market, capable of decoding multiple video streams in different standards, and its unique, scalable design achieves high performance levels at very low clock rates (e. g. one 720p30fps stream at 33 MHz or one 8Kx4Kp@30fps, one 3D 4Kx2Kp@60fps or eight 1080p@60fps streams at only 300MHz).

    The cineramIC 4K-3D Video Decoder supports H.264, MPEG-1/2 and VC-1 video standards including H.264 MVC (Multi-view Video Coding) for three-dimensional (3D) imaging and high resolution JPEG still picture applications. Automatic multi-stream video decoding is supported for up to 16 streams without additional software interaction. Driver software performs set up and general control of tasks requiring fewer than 2 MIPS.



    The IP core reads the input stream from a buffer located in the system memory (SDRAM) and generates decoded video in YCbCr 4:2:0 and 4:2:2 (JPEG) formats. The output pictures are stored in the decoded picture buffer area within the system memory.

    Optimized for high-performance 3D video decoding applications, the cineramIC 4K-3D Video Decoder is based on an architecture that implements pipelining and parallelism on different levels with a combination of software and hardware components. The hardware is composed of three main blocks, the Stream Interpreter, the Multi-pipeline Scheduler and the scalable Multi-Standard Video Decoding Engine. In order to achieve maximum performance, all blocks work in parallel.

    The cineramIC 4K-3D Video Decoder IP core can satisfy a wide range of applications and technologies-achieving optimal performance at low cost and low power consumption. Its interfaces can be easily integrated into system-on-chip (SoC) designs and the scalable design allows system developers to optimize the SoC based on their specific application requirements.

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